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HD64F3664FP bảng dữ liệu(PDF) 85 Page - Renesas Technology Corp |
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HD64F3664FP bảng dữ liệu(HTML) 85 Page - Renesas Technology Corp |
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85 / 444 page ![]() Section 3 Exception Handling Rev. 6.00 Mar. 24, 2006 Page 57 of 412 REJ09B0142-0600 Bit Bit Name Initial Value R/W Description 0 IRRl0 0 R/W IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 6 1 1 Reserved These bits are always read as 1. 5 IWPF5 0 R/W WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF5 is cleared by writing 0. 4 IWPF4 0 R/W WKP4 Interrupt Request Flag [Setting condition] When WKP4 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF4 is cleared by writing 0. 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. |
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