HD64F3664FP datasheet(80/444 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Mar. 24, 2006 Page 52 of 412

REJ09B0142-0600

Table 3.1

Exception Sources and Vector Address

Relative Module

Exception Sources

Vector

Number

Vector Address

Priority

RES pin

Watchdog timer

Reset

H'0000 to H'0001

High



Reserved for system use

1 to 6

H'0002 to H'000D

External interrupt

NMI

H'000E to H'000F

Trap instruction (#0)

H'0010 to H'0011

(#1)

H'0012 to H'0013

(#2)

H'0014 to H'0015

CPU

(#3)

H'0016 to H'0017

Address break

Break conditions satisfied

H'0018 to H'0019

CPU

Direct transition by executing the

SLEEP instruction

H'001A to H'001B

IRQ0

H'001C to H'001D

IRQ1

H'001E to H'001F

IRQ2

H'0020 to H'0021

IRQ3

H'0022 to H'0023

External interrupt

WKP

H'0024 to H'0025

Timer A

Overflow

H'0026 to H'0027



Reserved for system use

H'0028 to H'0029

Timer W

Input capture A/compare match A

Input capture B/compare match B

Input capture C/compare match C

Input capture D/compare match D

Timer W overflow

H'002A to H'002B

Timer V

Timer V compare match A

Timer V compare match B

Timer V overflow

H'002C to H'002D

SCI3

SCI3 receive data full

SCI3 transmit data empty

SCI3 transmit end

SCI3 receive error

H'002E to H'002F

IIC

Data transfer end

Address inequality

Stop conditions detected

H'0030 to H'0031

A/D converter

A/D conversion end

H'0032 to H'0033

Low

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