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Giải thích chi tiết về linh kiện  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 41 of 412
REJ09B0142-0600
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock (
φ) or a subclock (φ
SUB). The period from a rising
edge of
φ or φ
SUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T1 state
Bus cycle
T2 state
Internal address bus
φ or φ
SUB
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
Figure 2.9 On-Chip Memory Access Cycle



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