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H8S2245 bảng dữ liệu(PDF) 811 Page - Renesas Technology Corp |
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H8S2245 bảng dữ liệu(HTML) 811 Page - Renesas Technology Corp |
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811 / 818 page ![]() Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Rev.3.00 Mar. 26, 2007 Page 769 of 772 REJ09B0355-0300 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown figure F.1. RES must remain low until STBY goes low (delay from STBY fall to RES rise: minimum 0 ns). STBY RES t1 ≥ 10 tcyc t2 ≥ 0 ns Figure F.1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high, and execute a power-on reset. tNMIRH tOSC t ≥ 100 ns STBY RES NMI Figure F.2 Timing of Recovery from Hardware Standby Mode |
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