H8S2245 datasheet(373/818 Pages) RENESAS

tên linh kiện	H8S2245

Giải thích chi tiết về linh kiện	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 331 of 772

REJ09B0355-0300

When TGR is an input capture register: Figure 9.20 shows an operation example in which

TGRA has been designated as an input capture register, and buffer operation has been designated

for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges

have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of

input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.

TCNT value

H'09FB

H'0000

TGRC

Time

H'0532

TIOCA

TGRA

H'0F07

H'0532

H'0F07

H'0532

H'0F07

H'09FB

Figure 9.20 Example of Buffer Operation (2)

9.4.5

PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be

selected as the output level in response to compare match of each TGR.

Designating TGR compare match as the counter clearing source enables the period to be set in that

also possible.

There are two PWM modes, as described below.

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