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M32C83T bảng dữ liệu(PDF) 140 Page - Renesas Technology Corp

tên linh kiện M32C83T
Giải thích chi tiết về linh kiện  16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  527 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C83T bảng dữ liệu(HTML) 140 Page - Renesas Technology Corp

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Page 117
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Setting Value
DMA Request Cause
b4 b3 b2 b1 b0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
DMA0
Falling edge of INT0
Both edges of INT0
DMA1
DMA2
Falling edge of INT2
Both edges of INT2
DMA3
Falling edge of INT3(1)
Both edges of INT3(1)
Software Trigger
Timer A0 Interrupt Request
Timer A1 Interrupt Request
Timer A2 Interrupt Request
Timer A3 Interrupt Request
Timer A4 Interrupt Request
Timer B0 Interrupt Request
Timer B1 Interrupt Request
Timer B2 Interrupt Request
Timer B3 Interrupt Request
Timer B4 Interrupt Request
Timer B5 Interrupt Request
UART0 Transmit Interrupt Request
UART0 Receive or ACK Interrupt Request(3)
UART1 Transmit Interrupt Request
UART1 Receive or ACK Interrupt Request(3)
UART2 Transmit Interrupt Request
UART2 Receive or ACK Interrupt Request(3)
UART3 Transmit Interrupt Request
UART3 Receive or ACK Interrupt Request(3)
UART4 Transmit Interrupt Request
UART4 Receive or ACK Interrupt Request(3)
Falling edge of INT1
Both edges of INT1
A/D0 Interrupt Request
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 4 Request
Intelligent I/O
Interrupt 5 Request
Intelligent I/O
Interrupt 6 Request
A/D1 Interrupt Request
Intelligent I/O
Interrupt 7 Request
Intelligent I/O
Interrupt 8 Request
Intelligent I/O
Interrupt 9 Request(4)
Intelligent I/O
Interrupt 10 Request(5)
Intelligent I/O
Interrupt 11 Request(6)
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 1 Request
A/D0 Interrupt request
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
Intelligent I/O
Interrupt 4 Request
Intelligent I/O
Interrupt 5 Request
Intelligent I/O
Interrupt 6 Request
Intelligent I/O
Interrupt 7 Request
Intelligent I/O
Interrupt 8 Request
A/D1 Interrupt Request
Intelligent I/O
Interrupt 9 Request(4)
Intelligent I/O
Interrupt 10 Request(5)
Intelligent I/O
Interrupt 11 Request(6)
Intelligent I/O
Interrupt 0 Request
Intelligent I/O
Interrupt 1 Request
Intelligent I/O
Interrupt 2 Request
Intelligent I/O
Interrupt 3 Request
(Note 2)
(Note 2)
NOTES:
1. If the INT3 pin is used as data bus in the memory expansion mode or microprocessor mode, a DMA3 interrupt
request cannot be generated by an input signal to the INT3 pin.
2. The falling edge and both edges of input signal into the INTj pin (j = 0 to 3) cause a DMA request. The INT interrupt
(the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa.
3. The UkSMR register and UkSMR2 register (k = 0 to 4) switch the UARTj receive to ACK or ACK to UARTk receive.
4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request.
5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request.
6. The same setting is used to generate an intelligent I/O interrupt 11 request and a CAN interrupt 2 request.
Table 12.2 DMiSL Register (i = 0 to 3) Function



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