7641 datasheet(18/138 Pages) RENESAS

18 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 18 of 135

REJ03B0191-0400

Fig. 14 Port block diagram (3)

HOLD

HLDA

(13) Port P71

Data bus

Direction

Port latch

HOLD function enable bit

HOLD function

enable bit

(15) Port P73

IBF1 output enable bit

Data bus buffer function

select bit

HOLD function

enable bit

Direction

Port latch

IBF1 output

Data bus

(17) Port P80

Direction

Port latch

Data bus

SRDY output select bit

(UART2) Transmit enable bit

SRDY output

SPI mode select bit

Control for SPI

compatible mode

(UART2) UTXD2 output

Data bus buffer function select bit

(14) Port P72

Data bus

Direction

Port latch

Data bus buffer

function select bit

Data bus buffer function select bit

(16) Port P74

Data bus

Direction

Port latch

OBF1 output enable bit

OBF1 output

(18) Port P81

Data bus

Direction

Port latch

(Serial I/O) Internal synchronous clock select bits

Serial I/O port select bit

(UART2) Receive enable bit

(Serial I/O) Internal

synchronous clock

select bits

(UART2) Receive enable bit

(UART2) URXD2 input

Serial I/O clock input

Serial I/O clock output

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