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7641 bảng dữ liệu(PDF) 87 Page - Renesas Technology Corp

tên linh kiện 7641
Giải thích chi tiết về linh kiện  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PDF  138 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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7641 Group
Rev.4.00
Aug 28, 2006
page 87 of 135
REJ03B0191-0400
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AB15–AB8 delay time
AB15–AB8 valid time
AB7–AB0 delay time
AB7–AB0 valid time
WR delay time
WR valid time
RD delay time
RD valid time
SYNCOUT delay time
SYNCOUT valid time
DMAOUT delay time
DMAOUT valid time
RDY setup time
RDY hold time
HOLD setup time
HOLD hold time
HOLD “L” delay time
HOLD “H” delay time
Data bus setup time
Data bus hold time
Data bus delay time
Data bus valid time (Note 1)
EDMA delay time
EDMA valid time
WR pulse width
RD pulse width
AB15–AB8 valid time before WR
AB7–AB0 valid time before WR
AB15–AB8 valid time after WR
AB7–AB0 valid time after WR
AB15–AB8 valid time before RD
AB7–AB0 valid time before RD
AB15–AB8 valid time after RD
AB7–AB0 valid time after RD
RDY setup time before WR
RDY hold time after WR
RDY setup time before RD
RDY hold time after RD
Data bus setup time before RD
Data bus hold time after RD
Data bus delay time before WR
Data bus valid time after WR (Note 1)
EDMA delay time after WR
EDMA valid time after RD
USB output rise time, CL = 50 pF
USB output fall time, CL = 50 pF
tC(
φ)
tWH(
φ)
tWL(
φ)
td(
φ -AH)
tv(
φ -AH)
td(
φ -AL)
tv(
φ -AL)
td(
φ -WR)
tv(
φ -WR)
td(
φ -RD)
tv(
φ -RD)
td(
φ -SYNC)
tv(
φ -SYNC)
td(
φ -DMA)
tv(
φ -DMA)
tsu(RDY-
φ)
th(
φ -RDY)
tsu(HOLD-
φ)
th(
φ -HOLD)
td(
φ -HLDAL)
td(
φ -HLDAH)
tsu(DB-
φ)
th(
φ -DB)
td(
φ -DB)
tV(
φ -DB)
td(
φ -EDMA)
tv(
φ -EDMA)
tWL(WR) (Note 2)
tWL(RD) (Note 2)
td(AH-WR)
td(AL-WR)
tv(WR-AH)
tv(WR-AL)
td(AH-RD)
td(AL-RD)
tv(RD-AH)
tv(RD-AL)
tsu(RDY-WR)
th(WR-RDY)
tsu(RDY-RD)
th(RD-RDY)
tsu(DB-RD)
th(RD-DB)
td(WR-DB)
tv(WR-DB)
tv(WR-EDMA)
tv(RD-EDMA)
tr(D+), tr(D-)
tf(D+), tf(D-)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
83.33
0.5•tc(
φ) – 5
0.5•tc(
φ) – 5
5
5
3
3
4
5
21
0
21
0
7
0
13
4
0.5•tc(
φ) – 5
0.5•tc(
φ) – 5
0.5•tc(
φ) – 28
0.5•tc(
φ) – 30
0
0
0.5•tc(
φ) – 28
0.5•tc(
φ) – 30
0
0
27
0
27
0
13
0
10
2
2
4
4
Typ.
Max.
Symbol
Unit
Table 17 Timing requirements and switching characteristics in memory expansion and microprocessor modes
(Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
31
33
6
6
6
25
In Vcc = 5 V
25
25
22
9
20
20
20



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