7641 datasheet(63/138 Pages) RENESAS

63 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 63 of 135

REJ03B0191-0400

Status output signal.

OBF0 signal is output.

Status output signal.

IBF0 signal is output.

Chip select input.

This is used for selecting the data bus buffer, which is

selected at “L” level.

Address input.

This is used for selecting DBBSTS and DBBOUT

when the host CPU reads.

This is used for distinguishing command from data

when the host CPU writes.

This is a timing signal for reading data from the data

bus buffer to the host CPU.

This is a timing signal for writing data to the data bus

buffer by the host CPU.

Chip select input.

This is used for selecting the data bus buffer, which is

selected at “L” level.

Status output signal.

IBF1 signal is output.

Status output signal.

OBF1 signal is output.

P52/OBF0

Table 8 Function description of control I/O pins of master CPU bus interface

Name

OBF0

output

enable

bit

IBF0

output

enable

bit

OBF1

output

enable

bit

Input/

Output

Functions

OBF0

IBF1

output

enable

bit

Output

P53/IBF0

P54/S0

P55/A0

P56/R (E)

P57/W (R/W)

P72/S1

P73/IBF1/HLDA

P74/OBF1

IBF0

R (E)

W (R/W)

IBF1

OBF1

—

Output

Input

Output

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