7641 datasheet(64/138 Pages) RENESAS

64 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 64 of 135

REJ03B0191-0400

Fig. 57 Special count source generator block diagram

COUNT SOURCE GENERATOR

The 7641 Group has a built-in special count source generator,

SCSG. This generator consists of two 8-bit timers: SCSG1 and

SCSG2. The output of the special count source generator can be

used as a clock source for the timer X, serial I/O and two UARTs.

SCSG Operation

Timers SCSG1 and SCSG2 are both down count timers. When the

count reaches “0”, an underflow occurs at the next count source

rising edge and the contents of the corresponding timer latch are

loaded to the timer. The division ratio of each SCSG-x timer is

given by 1 / (n+1), where “n” is the value set to the SCSG-x timer.

The output of Timer SCSG1 is ANDed with the original clock (

φ) to

make a count source for Timer SCSG2.

The SCSG output is Clock SCSGCLK. The frequency is calculated

as follows:

SCSGCLK =

φ ✕ {n1 / (n1+1)} ✕ {1 / (n2+1)}

n1: value set to SCSG1

n2: value set to SCSG2

If the SCSG1 Count Stop Bit (SCSGM1) is set to “1”, or Timer

SCSG1 is set to “0”, the SCSG1 count stops. When this happens,

the count source for Timer SCSG2 becomes

φ.

Data Write Control

When the SCSG1 Data Write Control Bit or SCSG2 Data Write

Control Bit is set to “0”, and data is written to the SCSG-x timer;

the data is written to the corresponding latch and timer at the

same time. When that bit is set to “1”, the data is only written to

the latch.

SCSGCLK

SCSG1 count stop bit

SCSGCLK output control bit

SCSG1 Timer Reload Latch

SCSG1 Timer (8)

SCSG1 data write control bit

SCSG2 data write control bit

SCSG2 Timer Reload Latch

SCSG2 Timer (8)

SCSGCLK output control bit

SCSG1 count stop bit

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