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MSC7119 bảng dữ liệu(PDF) 45 Page - Freescale Semiconductor, Inc |
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MSC7119 bảng dữ liệu(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 60 page ![]() Hardware Design Considerations MSC7119 Data Sheet, Rev. 8 Freescale Semiconductor 45 3.2.2.3 Case 3 The power-up sequence is as follows: 1. Turn on the VDDIO (3.3 V) supply first. 2. Turn on the VDDC (1.2 V) supply second. 3. Turn on the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (third). Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms. The power-down sequence is as follows: 1. Turn off the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (first). 2. Turn off the VDDC (1.2 V) supply second. 3. Turn of the VDDIO (3.3 V) supply third (last). Use the following guidelines: • Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms. • Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for power-up and power-down. • Refer to Figure 32 for relative timing for Case 3. Figure 32. Voltage Sequencing Case 3 Time Ramp-down Ramp-up VDDIO = 3.3 V VDDM = 2.5 V VDDC = 1.2 V VREF = 1.25 V <10 ms <10 ms <10 ms <10 ms |
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