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MSC7119 bảng dữ liệu(PDF) 36 Page - Freescale Semiconductor, Inc

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MSC7119 bảng dữ liệu(HTML) 36 Page - Freescale Semiconductor, Inc

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MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
36
2.5.8
I2C Timing
Table 26. I2C Timing
No.
Characteristic
Fast
Unit
Min
Max
450
SCL clock frequency
0
400
kHz
451
Hold time START condition
(SCL clock period/2) – 0.3
—
μs
452
SCL low period
(SCL clock period/2) – 0.3
—
μs
453
SCL high period
(SCL clock period/2) – 0.1
—
μs
454
Repeated START set-up time (not shown in figure)
2
× 1/FBCK
—
μs
455
Data hold time
0
—
μs
456
Data set-up time
250
—
ns
457
SDA and SCL rise time
—
700
ns
458
SDA and SCL fall time
—
300
ns
459
Set-up time for STOP
(SCL clock period/2) – 0.7
—
μs
460
Bus free time between STOP and START
(SCL clock period/2) – 0.3
—
μs
Note:
SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance
on SDA and SCL is 400 pF.
Figure 20. I2C Timing Diagram
SCL
SDA
Data Byte
Start Condition
Stop Condition
A
C
K
78
9
456
1
2
3
Start Condition
458
458
457
457
460
459
451
452
453
SCL
SDA
Data Byte
Start Condition



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