MSC7119 datasheet(24/60 Pages) FREESCALE

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MSC7119 Data Sheet, Rev. 8

Electrical Characteristics

Freescale Semiconductor

2.5.3

Reset Timing

The MSC7119 device has several inputs to the reset logic. All MSC7119 reset sources are fed into the reset controller, which

takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause

a reset. Table 14 describes the reset sources.

Table 15 summarizes the reset actions that occur as a result of the different reset sources.

2.5.3.1

Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after

external power to the MSC7119 reaches at least 2/3 VDD.

Table 14. Reset Sources

Name

Direction

Description

Power-on reset

(PORESET)

Input

Initiates the power-on reset flow that resets the MSC7119 and configures various attributes of the

MSC7119. On PORESET, the entire MSC7119 device is reset. SPLL and DLL states are reset,

HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The

system is configured only when PORESET is asserted.

External Hard

reset (HRESET)

Input/ Output

Initiates the hard reset flow that configures various attributes of the MSC7119. While HRESET is

asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400

extended core is reset.

Software

watchdog reset

Internal

When the MSC7119 watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

Bus monitor

reset

Internal

When the MSC7119 bus monitor count reaches zero, a bus monitor hard reset is asserted. The

enabled bus monitor event then generates an internal hard reset sequence.

JTAG EXTEST,

CLAMP, or

HIGHZ command

Internal

When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic

asserts an internal reset signal that generates an internal soft reset sequence.

Table 15. Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On Reset

(PORESET)

Hard Reset

(HRESET)

Soft Reset

(SRESET)

External only

External or

Internal (Software

Watchdog or Bus

Monitor)

JTAG Command:

EXTEST, CLAMP,

or HIGHZ

Configuration pins sampled (refer to Section 2.5.3.1 for

details).

Yes

PLL and clock synthesis states Reset

Yes

HRESET Driven

Yes

Software watchdog and bus time-out monitor registers

Yes

Clock synthesis modules (STOPCTRL, HLTREQ, and

HLTACK) reset

Yes

Extended core reset

Yes

Peripheral modules reset

Yes

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