STPCELITE datasheet(60/87 Pages) STMICROELECTRONICS

60 / 87 page

DESIGN GUIDELINES

60/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

6.2. STPC CONFIGURATION

The STPC is a very flexible product thanks to

decoupled clock domains and to strap options

enabling a user-optimized configuration.

As some trade off are often necessary, it is

important to do an analysis of the application

needs prior to design a system based on this

product. The applicative constraints are usually

the following:

- CPU performance

- graphics / video performances

- power consumption

- PCI bandwidth

- booting time

- EMC

Some other elements can help to tune the choice:

- Code size of CPU Consuming tasks

- Data size and location

On the STPC side, the configurable parameters

are the following:

- synchronous / asynchronous mode

- HCLK speed

- MCLK speed

- CPU clock ratio (x1, x2)

- Local Bus / ISA bus

6.2.1. LOCAL BUS / ISA BUS

The selection between the ISA bus and the Local

Bus is relatively simple. The first one is a standard

bus but slow. The Local Bus is fast and

programmable but doesn't support any DMA nor

external master mechanisms. The Table 6-1

below summarize the selection:

Before implementing a function requiring DMA

capability on the ISA bus, it is recommended to

check if it exists on PCI, or if it can be

implemented differently, in order to use the local

bus mode.

6.2.2. CLOCK CONFIGURATION

The CPU clock and the memory clock are

independent unless the "synchronous mode"

strap option is set (see the STRAP OPTIONS

chapter). The potential clock configurations are

then relatively limited as listed in Table 6-2.

The

advantage

the

synchronous

mode

compared to the asynchronous mode is a lower

latency when accessing SDRAM from the CPU or

the PCI (saves 4 MCLK cycles for the first access

of the burst). For the same CPU to Memory

transfer performance, MCLK as to be roughly

higher by 20MHz between SYNC and ASYNC

modes

(example:

66MHz

SYNC

96MHz

ASYNC).

In all cases, use SDRAM with CAS Latency

equals to 2 (CL2) for the best performances.

The advantage of the asynchronous mode is the

capability to reprogram the MCLK speed on the

fly. This could help for applications were power

consumption must be optimized.

Regarding PCI bandwidth, the best is to have

HCLK at 100MHz as it gives twice the bandwidth

compared to HCLK at 66MHz.

The last, and more complex, information to

consider is the behaviour of the software. In case

high CPU or FPU computation is needed, it is

sometime better to be in DX2-133/MCLK=66

synchronous mode than DX2-133/MCLK=100

asynchronous mode. This depends on the locality

of the number crunching code and the amount of

data manipulated.

The Table 6-3 below gives some examples. The

right column correspond to the configuration

number as described in Table 6-2:

Obviously, the values for HCLK or MCLK can be

reduced compared to Table 6-2 in case there is no

need to push the device at its limits, or when

avoiding to use specific frequency ranges (FM

radio band for example).

Table 6-1. Bus mode selection

Need

Selection

Legacy I/O device (Floppy, ...), Super I/O

ISA Bus

DMA capability (Soundblaster)

ISA Bus

Flash, SRAM, basic I/O device

Local Bus

Fast boot

Local Bus

Boot flash of 4MB or more

Local Bus

Programmable Chip Select

Local Bus

Table 6-2. Main STPC modes

CMode

HCLK

MHz

CPU clock

clock ratio

MCLK

MHz

Synchronous

133 (x2)

Asynchronous

133 (x2)

100

Synchronous

100

100 (x1)

100

Table 6-3. Clock mode selection

Constraints

Need CPU power

Critical code fits into L1 cache

Need CPU power

Code or data does not fit into L1 cache

Need high PCI bandwitdh

Need flexible SDRAM speed

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