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STPCELITE bảng dữ liệu(PDF) 8 Page - STMicroelectronics

tên linh kiện STPCELITE
Giải thích chi tiết về linh kiện  X86 Core General Purpose PC Compatible System - on - Chip
PDF  87 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPCELITE bảng dữ liệu(HTML) 8 Page - STMicroelectronics

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GENERAL DESCRIPTION
8/87
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1.4. CLOCK TREE
The STPC Elite integrates many features and
generates all its clocks from a single 14MHz
oscillator. This results in multiple clock domains as
described in Figure 1-2.
The speed of the PLLs is either fixed (DEVCLK),
either programmable by strap option (HCLK)
either
programmable
by
software
(GPCLK,
MCLK). When in synchronized mode, MCLK
speed is fixed to HCLKO speed and HCLKI is
generated from MCLKI.
Figure 1-2. STPC Elite clock architecture
IPC
SDRAM controller
North Bridge
14.31818 MHz
XTALO
XTALI
OSC14M
ISACLK
1/4
GPCLK
GPCLK
PLL
(14MHz)
1/2
HCLK
PLL
PCICLKI
PCICLKO
South Bridge
1/2
1/3
HCLK
MCLK
PLL
MCLKI
MCLKO
CPU
x1
x2
Local Bus
Host
ISA
HCLKI
HCLKO



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