SABRE-LL-I datasheet(128/141 Pages) STMICROELECTRONICS

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Serial interface

SABRE-LL-I

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Figure 43.

SPI read transaction

23.2

Write transaction

A write transaction (see Figure 44) is always started by the master lowering the signal on

nSS pin. The other bits are then sent on the mosi pin with this order:

7-bit representing the address of the register that must be written (MSB first [A6…A0]);

2-bit that must be “01” for a read transaction;

2-bit representing S.A.B.Re IC address;

1-bit reserved for future use that must be set at “0”.

The data to be written (MSB first D15…D0) are then read from mosi pin. The length of data

field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched

on rising edge of the nSS line.

Figure 44.

SPI write transaction

The SPI input and output timing definitions are shown in the following tables:

nSS

sclk

mosi

miso

D15

Address field

Data Field

Control

Field

address

High Impedance

nSS

sclk

mosi

miso

D15

Address field

Data Field

Control

Field

addres

High Impedance

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