SABRE-LL-I datasheet(65/141 Pages) STMICROELECTRONICS

65 / 141 page

SABRE-LL-I

Power bridges

65/141

Here after are summarized the primary features of the regulator(s):

–

Synchronous rectification

–

Automatic low side disabling when current in the inductance reaches 0 to optimize

efficiency at low load

–

Pulse skipping control

–

Internally generated PWM

–

Cycle by cycle current limiting using internal current sensor

–

Protected against load short circuit

–

Soft start circuitry

–

Under voltage signal (both continuous and latched) accessible through serial

interface.

Figure 17.

Regulator block diagram

Depending on the load current, there could be the necessity to add a Schottky diode on

output to reduce internal thermal dissipation. This diode must be placed near to the pin and

must be fast recovery and low series resistance type.

For detail about pulse skipping please refer to main switching regulator paragraph.

The output voltage will be externally set by a divider network connected on feedback pin. To

reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to

switch between four regulator feedback voltage references (and, as a consequence, four

under-voltage thresholds) using serial interface. The feedback reference voltage is selected

Vout

Vsupply

Half Bridge OUT

High Side

Driver

Control

Logic

CurrentSense

Charge pump Voltage

GPIO USED as FB

Voltage

Loop Control

Regulator Ref

Under voltage

Threshold

Filter

Low Side

Driver

From Central Logic

Regulator Freq

To Central Logic

Obtained using spare analog

/digital blocks

BridgeSense

Vref= 0.8V

N.C.

Vref=3V

SelFBRef

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