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OR4 bảng dữ liệu(PDF) 104 Page - Lattice Semiconductor

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104
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information (continued)
Table 65. Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins
(continued)
DIN
I
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
DOUT
O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.
I/O After configuration, DOUT is a user-programmable I/O pin.*
TESTCFG
I
During configuration this pin should be held high, to allow configuration to occur. A pull up is
enabled during configuration.
I/O After configuration, TESTCFG is a user programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.



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