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Data Sheet

May, 2006

ORCA® Series 4 FPGAs

www.latticesemi.com

1

or4e_05

other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to

change without notice.

Introduction

Built on the Series 4 reconﬁgurable embedded sys-

tem-on-a-chip (SoC) architecture, Lattice introduces

its new family of generic Field-Programmable Gate

Arrays (FPGAs). The high-performance and highly

versatile architecture brings a new dimension to

bringing network system designs to market in less

time than ever before. This new device family offers

many new features and architectural enhancements

not available in any earlier FPGA generations. Bring-

ing together highly ﬂexible SRAM-based programma-

ble logic, powerful system features, a rich hierarchy

of routing and interconnect resources, and meeting

multiple interface standards, the Series 4 FPGA

accommodates the most complex and high-perfor-

mance intellectual property (IP) network designs.

Programmable Features

■

High-performance platform design:

— 0.16 μm 7-level metal technology.

— Internal performance of >250 MHz.

— I/O performance of >420 MHz.

— Meets multiple I/O interface standards.

— 1.5 V operation (30% less power than 1.8 V

operation) translates to greater performance.

■

Traditional I/O selections:

— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)

I/Os.

— Per pin-selectable I/O clamping diodes provide

3.3 V PCI compliance.

— Individually programmable drive capability:

24 mA sink/12 mA source, 12 mA sink/6 mA

source, or 6 mA sink/3 mA source.

— Two slew rates supported (fast and slew-lim-

ited).

— Fast-capture input latch and input ﬂip-ﬂop

(FF)/latch for reduced input setup time and zero

hold time.

— Fast open-drain drive capability.

— Capability to register 3-state enable signal.

— Off-chip clock drive capability.

— Two-input function generator in output path.

■

New programmable high-speed I/O:

— Single-ended: GTL, GTL+, PECL, SSTL3/2

(class I and II), HSTL (Class I, III, and IV), ZBT,

and DDR.

— Double-ended: LDVS, bused-LVDS, and

LVPECL. Programmable (on/off) internal parallel

termination (100 Ω) also supported for these

I/Os.

Table 1. ORCA Series 4—Available FPGA Logic

* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:

minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum

system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.

Note: Devices are not pinout compatible with ORCA Series 2/3.

Device

Rows

Columns

PFUs

User I/O

LUTs

EBR

Blocks

EBR Bits

(K)

Usable*

Gates (K)

OR4E02

26

24

624

405

4,992

8

74

201—397

OR4E04

36

1,296

466

10,368

12

111

333—643

OR4E06

46

44

2,024

466

16,192

16

148

471—899

Số phần tương tự - OR4

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Advanced Energy Industr...	OR4000E	212Kb / 4P	DELIVERING PRECISION TEMPERATURE MEASUREMENT ACROSS MULTIPLE PROCESSES AND SUBSTRATES
Agere Systems	OR4E10	3Mb / 124P	Field-Programmable Gate Arrays December 2000
	OR4E2	3Mb / 124P	Field-Programmable Gate Arrays December 2000
	OR4E4	3Mb / 124P	Field-Programmable Gate Arrays December 2000
	OR4E6	3Mb / 124P	Field-Programmable Gate Arrays December 2000

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	A1020B-PL68C	1Mb / 98P	HiRel FPGAs
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