OR4 datasheet(29/152 Pages) LATTICE

29 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Embedded Block RAM (continued)

0308(F)

Figure 21. EBR Read and Write Cycles with Write Through and Nonregistered Read Port

Table 9. FIFO Signals

Port Signals

I/O

Function

AR0[5:0]

Programs FIFO ﬂags. Used for partially empty ﬂag size.

AR1[9:0]

Programs FIFO ﬂags. Used for partially full ﬂag size.

Full Flag.

PFF

Partially Full Flag.

PEF

Partially Empty Flag.

Empty Flag.

D0[17:0]

Data inputs for all conﬁgurations.

D1[17:0]

Data inputs for 256x36 conﬁgurations only.

CKW[0:1]

Positive-edge write port clock. Port 1 only used for 256x36 conﬁgurations.

CKR[0:1]

Positive-edge read port clock. Port 1 only used for 256x36 conﬁgurations.

CSW[1:0]

Active-high write enable. Port 1 only used for 256x36 conﬁgurations.

CSR[1:0]

Active-high read enable. Port 1 only used for 256x36 conﬁgurations.

RESET

Active-low Resets FIFO pointers.

Q0[17:0]

Data outputs for all conﬁgurations.

Q1[17:0]

Data outputs for 256x36 conﬁgurations.

CKWPH

CKWPL

CSWSU

CSWH

AWH

DSU

BWSU

BWH

AWSU

CKWQ

AQH

CKW

CSW

OR4 bảng dữ liệu(PDF) 29 Page - Lattice Semiconductor

OR4 bảng dữ liệu(HTML) 29 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL