OR4 datasheet(83/152 Pages) LATTICE

83 / 152 page

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Timing Characteristics (continued)

Table 43. PIO Input Buffer Timing Characteristics

OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +85 ˚C

OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +100 ˚C

Notes:

The delays for all input buffers assume an input rise/fall time of <1 V/ns.

The values in the above table should be used to modify the information in Table 46 through Table 52, which are all based on LVTTL input timing.

Parameter

Symbol

Speed

Unit

-1

-2

-3

Min

Max

Min

Max

Min

Max

Input Delays

Input Rise Time

IN_RIS

—

100

—

100

—

100

Input Fall Time

IN_FAL

—

100

—

100

—

100

Input Delay Adjustments from LVTTL:

LVCMOS2 (2.5 V)

LVCMOS18 (1.8 V)

LVDS

LVDSE

LVPECL

PCI_33 (3.3 V)

PCI_66 (3.3 V)

GTL

GTLP (GTL+)

HSTL_I

HSTL_II

HSTL_III

HSTL_IV

SSTL2_I

SSTL2_II

SSTL3_I

SSTL3_II

PECL

IN_LVCMOS25

IN_LVCMOS15

IN_LVDS

IN_LVDSE

IN_LVPECL

IN_PCI_33

IN_PCI_66

IN_GTL

IN_GTLP

IN_HSTL_I

IN_HSTL_II

IN_HSTL_III

IN_HSTL_IV

IN_SSTL2_I

IN_SSTL2_II

IN_SSTL3_I

IN_SSTL3_II

IN_PECL

—

0.54

1.91

–0.04

0.30

–0.31

0.59

5.32

1.87

–0.05

–0.20

2.28

0.78

0.83

—

0.44

1.50

0.10

0.32

–0.21

0.50

4.68

2.04

–0.06

–0.13

1.66

0.69

0.72

—

0.40

1.36

0.09

0.29

–0.19

0.45

4.26

1.86

–0.06

–0.12

1.51

0.63

0.65

OR4 bảng dữ liệu(PDF) 83 Page - Lattice Semiconductor

OR4 bảng dữ liệu(HTML) 83 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL