OR4 datasheet(102/152 Pages) LATTICE

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102

Lattice Semiconductor

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Pin Information (continued)

Table 65. Pin Descriptions

(continued)

Symbol

I/O

Description

Special-Purpose Pins

M[3:0]

During powerup and initialization, M0—M3 are used to select the conﬁguration mode with their val-

ues latched on the rising edge of INIT. During conﬁguration, a pull-up is enabled.

I/O After conﬁguration, these pins are user-programmable I/O.*

PLL_CK[0:7][TC]

Semi-dedicated PLL clock pins. During conﬁguration they are 3-stated with a pull up.

I/O These pins are user-programmable I/O pins if not used by PLLs after conﬁguration.

P[TBLR]CLK[1:0][TC]

Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.

I/O After conﬁguration these pins are user programmable I/O, if not used for clock inputs.

TDI, TCK, TMS

Before conﬁguration these pins are test data in, test clock, and test mode select inputs. If bound-

ary-scan is enabled after conﬁguration, these pins remain test data in, test clock, and test mode

select inputs. If boundary-scan is not enabled after conﬁguration, all boundery-scan functions are

inhibited once conﬁguration is complete. During conﬁguration, either TCK or TMS must be held at a

logic 1. Each pin has a pull-up enabled during conﬁguration. To enable boundary-scan after conﬁg-

uration, a BNDSCAN library element must be instantiated in the user's design and the appropriate

bitgen setting must be enabled in the ispLEVER software.

I/O After conﬁguration, these pins are user-programmable I/O in boundary scan is not used.*

RDY/BUSY/RCLK

O During conﬁguration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be

written to the FPGA. If a read operation is done when the device is selected, the same status is also

available on D7 in asynchronous peripheral mode.

During the master parallel conﬁguration mode, RCLK is a read output signal to an external memory.

This output is not normally used.

I/O After conﬁguration this pin is a user-programmable I/O pin.*

HDC

O High during conﬁguration is output high until conﬁguration is complete. It is used as a control output,

indicating that conﬁguration is not complete.

I/O After conﬁguration, this pin is a user-programmable I/O pin.*

LDC

O Low during conﬁguration is output low until conﬁguration is complete. It is used as a control output,

indicating that conﬁguration is not complete.

I/O After conﬁguration, this pin is a user-programmable I/O pin.*

INIT

I/O INIT is a bidirectional signal before and during conﬁguration. During conﬁguration, a pull-up is

enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT

is held low during power stabilization and internal clearing of memory. As an active-low input, INIT

holds the FPGA in the wait-state before the start of conﬁguration.

After conﬁguration, this pin is a user-programmable I/O pin.*

CS0, CS1

CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor conﬁgu-

ration modes. The FPGA is selected when CS0 is low and CS1 is high. During conﬁguration, a pull-

up is enabled.

I/O After conﬁguration, if MPI is not used, these pins are user-programmable I/O pins.*

RD/MPI_STRB

RD is used in the asynchronous peripheral conﬁguration mode. A low on RD changes D[7:3] into a

status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides.

This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready,

and a low indicates busy.

I/O After conﬁguration, if the MPI is not used, this pin is a user-programmable I/O pin.*

* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conﬁguration pins (and the activation of all

user I/Os) is controlled by a second set of options.

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