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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ECP2 bảng dữ liệu(PDF) 284 Page - Lattice Semiconductor |
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ECP2 bảng dữ liệu(HTML) 284 Page - Lattice Semiconductor |
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284 / 386 page  4-183 Pinout Information Lattice Semiconductor LatticeECP2/M Family Data Sheet U10 NC - NC - U23 NC - NC - V10 NC - NC - W7 NC - NC - AB21 PB69B 4 BDQ69 C NC - AC20 PB58A 4 BDQ60 T NC - AC21 PB63A 4 BDQ60 T NC - AC22 PB69A 4 BDQS69**** T NC - AC23 PB71A 4 BDQ69 T NC - AC25 PB71B 4 BDQ69 C NC - AD26 PB70B 4 BDQ69 C NC - W20 PB72B 4 BDQ69 C NC - H7 L_VCCPLL - L_VCCPLL - K6 L_VCCPLL - L_VCCPLL - P7 L_VCCPLL - L_VCCPLL - R8 L_VCCPLL - L_VCCPLL - V18 R_VCCPLL - R_VCCPLL - P20 R_VCCPLL - R_VCCPLL - J17 R_VCCPLL - R_VCCPLL - G19 R_VCCPLL - R_VCCPLL - * Supports true LVDS. Other differential signals must be emulated with external resistors. ** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant. *** For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices (ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100). ****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width. Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one connection with a package ball or pin. LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA LFE2M35E/SE LFE2M50E/SE Ball Number Ball/Pad Function Bank Dual Function Differential Ball/Pad Function Bank Dual Function Differential |
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