ECP2 datasheet(42/386 Pages) LATTICE

42 / 386 page

2-39

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-36. DQS Local Bus

Polarity Control Logic

In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and

the internal system clock (during the READ cycle) is unknown.

The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up

and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector

is used. This changes the edge on which the data is registered in the synchronizing registers in the input register

block. This requires evaluation at the start of each READ cycle for the correct clock polarity.

Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects the ﬁrst DQS rising edge after the pre-

amble state. This signal is used to control the polarity of the clock to the synchronizing registers.

sysIO

Buffer

DDR

Datain

PAD

CLK1

CEI

PIO

sysIO

Buffer

GSR

DQS

To Sync

Reg.

DQS

To DDR

Reg.

DQS

Strobe

PAD

PIO

DQSDEL

Polarity Control

Logic

DQS

Calibration bus

from DLL

DQSXFER

Output

Input

DQSXFERDEL*

DQSXFER

DCNTL[6:0]

*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.

DCNTL[6:0]

ECLK1

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