ECP2 datasheet(10/386 Pages) LATTICE

10 / 386 page

2-7

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-5. General Purpose PLL (GPLL) Diagram

Standard PLL (SPLL)

Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but

without delay adjustment capability. SPLLs also provide different parametric speciﬁcations. For more information,

please see the list of additional technical documentation at the end of this data sheet.

Table 2-4 provides a description of the signals in the GPLL and SPLL blocks.

Table 2-4. GPLL and SPLL Blocks Signal Descriptions

Signal

I/O

Description

CLKI

Clock input from external pin or routing

CLKFB

PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock

(PIN or logic)

RST

“1” to reset PLL counters, VCO, charge pumps and M-dividers

RSTK

“1” to reset K-divider

CLKOS

PLL output clock to clock tree (phase shifted/duty cycle changed)

CLKOP

PLL output clock to clock tree (no phase shift)

CLKOK

PLL output to clock tree through secondary clock divider

LOCK

“1” indicates PLL LOCK to CLKI

DDAMODE

Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)

DDAIZR

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

DDAILAG

Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag

DDAIDEL[2:0]

Dynamic Delay Input

DPA MODES

DPA (Dynamic Phase Adjust/Duty Cycle Select) mode

DPHASE [3:0]

DPA Phase Adjust inputs

DDDUTY [3:0]

—

DPA Duty Cycle Select inputs

1. These signals are not available in SPLL.

Input Clock

Divider

(CLKI)

Feedback

Divider

(CLKFB)

Delay

Adjust

Voltage

Controlled

Oscillator

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

Secondary

Divider

(CLKOK)

CLKOS

CLKOK

CLKOP

LOCK

CLKFB

CLKI

RST

Dynamic Delay Adjustment

(from routing or external pin)

from CLKOP (PLL internal),

from clock net(CLKOP) or from

a user clock (pin or logic)

Dynamic Adjustment

PLLCAP External Pin

(Optional External Capacitor)

RSTK

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