ECP2 datasheet(119/386 Pages) LATTICE

119 / 386 page

4-18

Pinout Information

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

LatticeECP2M Power Supply and NC

Signal

256 fpBGA

484 fpBGA

VCC

G7, G9, H7, J10, K10, K8

J10, J11, J12, J13, K14, K9, L14, L9, M14, M9, N14,

N9, P10, P11, P12, P13

VCCIO0

B5, B9, E7, H9

VCCIO1

E10

D13, E16, H14

VCCIO2

E14, G12

E21, G18, J15, K19

VCCIO3

K12, M14

N19, P15, T18, V21

VCCIO4

M10, P12

AA18, R14, V16, W13

VCCIO5

M7, P5

AA5, R9, V7, W10

VCCIO6

K5, M3

N4, P8, T5, V2

VCCIO7

E3, G5

E2, G5, J8, K4

VCCIO8

T15

AA22, U19

VCCJ

VCCAUX

G8, H10, J7, K9

H11, H12, L15, L8, M15, M8, R11, R12

VCCPLL

G10

R8, H15, H8, R15

SERDES Power

C15, B15, C12, A12, C11, C10, C14, C13, B9,

C9, C5, C4, C8, C7, A6, C6, B3, C3

C22, B22, C19, A19, C18, C17, C21, C20, B16, C16,

C12, C11, C15, C14, A13, C13, B10, C10

GND

A1, A15, A16, A3, A9, B12, B6, E15, E2, H14,

H8, H9, J3, J8, J9, M15, M2, P9, R12, R5, T1,

T16

A1, A10, A16, A22, AA19, AA4, AB1, AB22, B13,

B19, B4, D16, D2, D21, D7, G19, G4, H10, H13, J14,

J9, K10, K11, K12, K13, K15, K20, K3, K8, L10, L11,

L12, L13, M10, M11, M12, M13, N10, N11, N12, N13,

N15, N20, N3, N8, P14, P9, R10, R13, T19, T4, W16,

W2, W21, W7, Y10, Y13

D10, D11, D12, D13, D14, D4, D5, D6, D7, E11,

E6, E8, E9, F10, F7, F8, F9

LFE2M20: D14, D15, E14, E15, F13, F14, F15, G12,

G13, G14, G15

LFE2M35: D14, D15, E14, E15, F13, F14, F15, G12,

G13, G14, G15, U6

LFE2M50: Y15, W15, AB20, AB21, AA20, AB19,

AB18, Y22, Y21, Y17, Y18, Y16, W17, Y19, Y20, W19,

W18, V17, V18, D15, G14, G15, D14, E15, E14, F15,

F14, F13, G12, G13

1. All grounds must be electrically connected at the board level. For fpBGA packages, the total number of GND balls is less than the actual

number of GND logic connections from the die to the common package GND plane.

2. NC pins should not be connected to any active signals, VCC or GND.

3. For package migration across device densities, the designer must comprehend the package pin requirements for the SERDES blocks. Spe-

ciﬁcally, the SERDES power pins of the largest density device must be accounted to accommodate migration to other smaller devices using

the same package. Please refer to technical note TN1160, LatticeECP2/M Density Migration, for more details.

ECP2 bảng dữ liệu(PDF) 119 Page - Lattice Semiconductor

ECP2 bảng dữ liệu(HTML) 119 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL