L6713A datasheet(9/64 Pages) STMICROELECTRONICS

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L6713A

Pin settings

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CS1+

Channel 1 current sense positive input.

Connect through an R-C filter to the phase-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

CS1-

Channel 1 current sense negative input.

Connect through a Rg resistor to the output-side of the channel 1 inductor.

See “Layout guidelines” Section for proper layout of this connection.

SS/ LTBG/

AMD

Soft-start oscillator, LTB gain and AMD selection pin.

It allows selecting between INTEL DACs and AMD DAC.

Short to SGND to select AMD DAC otherwise INTEL mode is selected.

When INTEL mode is selected trough this pin it is possible to select the soft-

start time and also the gain of LTB Technology™. See “Soft-start” Section” and

See “Load transient boost technologyTM” Section for details.

OVP

Over voltage programming pin. Internally pulled up by 12.5 µA (typ) to 5 V.

Leave floating to use built-in protection thresholds as reported into Table 12.

Connect to SGND through a ROVP resistor and filter with 100 pF (max) to set

the OVP threshold to a fixed voltage according to the ROVP resistor.

See “Over voltage and programmable OVP” Section Section for details.

VID_SEL

Intel mode. Internally pulled up by 12.5 µA (typ) to 5 V.

It allows selecting between VR10 (short to SGND, Table 8) or VR11 (floating,

See Table 7) DACs. See “Configuring the device” Section for details.

AMD mode. Not applicable. Needs to be shorted to SGND.

OCSET

Over current set pin.

Connect to SGND through a ROCSET resistor to set the OCP threshold. Connect

also a COCSET capacitor to set a delay for the OCP intervention.

See “Over current protection” Section for details.

FBG

Connect to the negative side of the load to perform remote sense.

See “Layout guidelines” Section for proper layout of this connection.

OSC/

FAULT

Oscillator pin.

It allows programming the switching frequency FSW of each channel: the

equivalent switching frequency at the load side results in being multiplied by the

phase number N.

Frequency is programmed according to the resistor connected from the pin vs.

SGND or VCC with a gain of 8 kHz/µA (see relevant section for details).

Leaving the pin floating programs a switching frequency of 200kHz per phase.

The pin is forced high (5 V) to signal an OVP FAULT: to recover from this

condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.

VID7/DVID

VID7 - Intel mode. See VID5 to VID0 section.

DVID - AMD mode. DVID output.

CMOS output pulled high when the controller is performing a D-VID transition

(with 32 clock cycle delay after the transition has finished). See “Dynamic VID

transitions” Section Section for details.

VID6

Intel mode. See VID5 to VID0 section.

AMD mode. Not applicable. Needs to be shorted to SGND.

Table 2.

Pin description (continued)

N°

Function

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