NRF52811-QCAA-R datasheet(367/444 Pages) NORDIC

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Peripherals

The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will

only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master

forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC

The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is

generated.

The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when

the TWI slave has stopped. The TWI slave will clear the 'TX prepared' flag and go back to the IDLE state

when it has stopped, see also Terminating an ongoing TWI transaction on page 369.

Each byte sent from the slave will be followed by an ACK/NACK bit sent from the master. The TWI master

will generate a NACK following the last byte that it wants to receive to tell the slave to release the bus so

that the TWI master can generate the stop condition. The TXD.AMOUNT register can be queried after a

transaction to see how many bytes were sent.

A typical TWI slave read command response is illustrated in The TWI slave responding to a read command

on page 367. Occurrence 2 in the figure illustrates clock stretching performed by the TWI slave following

a SUSPEND task.

ADDR

N-1

Stretch

Figure 140: The TWI slave responding to a read command

6.26.3 TWI slave responding to a write command

Before the TWI slave can respond to a write command the TWI slave must be configured correctly

and enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will

consume IIDLE.

A write command is started when the TWI master generates a start condition on the TWI bus, followed

by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The READ/WRITE bit is

followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the slave.

The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is

configured in the ADDRESS registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the write command if the address presented by the master

matches one of the addresses the slave is configured to listen for. The TWI slave will generate a WRITE

event if it acknowledges the write command.

The TWI slave is only able to detect a write command from the IDLE state.

The TWI slave will set an internal 'RX prepared' flag when the PREPARERX task is triggered.

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