NRF52811-QCAA-R7 datasheet(121/444 Pages) NORDIC

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Peripherals

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access

Field

Value ID

Value

Description

A-f

RW PIN[i] (i=0..31)

Set as input pin i

Input

Read: pin set as input

Output

Read: pin set as output

Clear

Write: writing a '1' sets pin to input; writing a '0' has no

effect

6.8.2.8 LATCH

Address offset: 0x520

Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access

Field

Value ID

Value

Description

A-f

RW PIN[i] (i=0..31)

Status on whether PINi has met criteria set in

PIN_CNFi.SENSE register. Write '1' to clear.

NotLatched

Criteria has not been met

Latched

Criteria has been met

6.8.2.9 DETECTMODE

Address offset: 0x524

Select between default DETECT signal behaviour and LDETECT mode

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access

Field

Value ID

Value

Description

RW DETECTMODE

Select between default DETECT signal behaviour and

LDETECT mode

Default

DETECT directly connected to PIN DETECT signals

LDETECT

Use the latched LDETECT behaviour

6.8.2.10 PIN_CNF[n] (n=0..31)

Address offset: 0x700 + (n × 0x4)

Configuration of GPIO pins

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

E E

D D D

C C B A

Reset 0x00000002

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Access

Field

Value ID

Value

Description

RW DIR

Pin direction. Same physical register as DIR register

Input

Configure pin as an input pin

Output

Configure pin as an output pin

RW INPUT

Connect or disconnect input buffer

Connect

Connect input buffer

4454_140 v1.0

121

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