HEF4013B

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 9 — 10 December 2015

8 of 16

NXP Semiconductors

HEF4013B

Dual D-type flip-flop

12. Waveforms

Set-up and hold times are shown as positive values but may be specified as negative values.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Measurement points are given in Table 9.

Fig 4.

Set-up time, hold time, minimum clock pulse width, propagation delays and transition times

Recovery times are shown as positive values but may be specified as negative values.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Measurement points are given in Table 9.

Fig 5.

nSD, nCD recovery time and pulse width

Table 9.

Measurement points

Supply voltage

Input

Output

VDD

VM

VM

VX

VY

5 V to 15 V

0.5VDD

0.5VDD

0.1VDD

0.9VDD