HEF4013B

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 9 — 10 December 2015

3 of 16

NXP Semiconductors

HEF4013B

Dual D-type flip-flop

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 = LOW-to-HIGH clock transition.

Fig 3.

Pin configuration

Table 2.

Pin description

Symbol

Pin

Description

1Q, 2Q

1, 13

true output

1Q, 2Q

2, 12

complement output

1CP, 2CP

3, 11

clock input (LOW to HIGH edge-triggered)

1CD, 2CD

4, 10

asynchronous clear-direct input (active HIGH)

1D, 2D

5, 9

data input

1SD, 2SD

6, 8

asynchronous set-direct input (active HIGH)

VSS

7

ground (0 V)

VDD

14

supply voltage

Table 3.

Function table[1]

Control

Input

Output

nSD

nCD

nCP

nD

nQ

nQ

H

L

XXH

L

L

H

XXL

H

H

H

XXH

H

LL



LLH

LL



HHL