HEF4013B

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 9 — 10 December 2015

6 of 16

NXP Semiconductors

HEF4013B

Dual D-type flip-flop

11. Dynamic characteristics

Table 7.

Dynamic characteristics

Tamb = 25 C; unless otherwise specified. For test circuit see Figure 6.

Symbol Parameter

Conditions

VDD

Extrapolation formula

Min

Typ

Max Unit

tPHL

HIGH to LOW

propagation delay

nCP to nQ, nQ;

see Figure 4

5 V

[1] 83 + 0.55

 C

L

-

110

220

ns

10 V

34 + 0.23

 C

L

-45

90

ns

15 V

22 + 0.16

 C

L

-30

60

ns

nSD to nQ

5 V

[1] 73 + 0.55

 C

L

-

100

200

ns

10 V

29 + 0.23

 C

L

-40

80

ns

15 V

22 + 0.16

 C

L

-30

60

ns

nCD to nQ

5 V

[1] 73 + 0.55

 C

L

-

100

200

ns

10 V

29 + 0.23

 C

L

-40

80

ns

15 V

22 + 0.16

 C

L

-30

60

ns

tPLH

LOW to HIGH

propagation delay

nCP to nQ, nQ;

see Figure 4

5 V

[1] 68 + 0.55

 C

L

-

95

190

ns

10 V

29 + 0.23

 C

L

-40

80

ns

15 V

22 + 0.16

 C

L

-30

60

ns

nSD to nQ

5 V

[1] 48 + 0.55

 C

L

-

75

150

ns

10 V

24 + 0.23

 C

L

-35

70

ns

15 V

17 + 0.16

 C

L

-25

50

ns

nCD to nQ

5 V

[1] 33 + 0.55

 C

L

-

60

120

ns

10 V

19 + 0.23

 C

L

-30

60

ns

15 V

12 + 0.16

 C

L

-20

40

ns

tt

transition time

see Figure 4

5 V

[1] 10 + 1.00

 C

L

-

60

120

ns

10 V

9 + 0.42

 C

L

-30

60

ns

15 V

6 + 0.28

 C

L

-20

40

ns

tsu

set-up time

nD to nCP;

see Figure 4

5 V

40

20

-

ns

10 V

25

10

-

ns

15 V

15

5

-

ns

th

hold time

nD to nCP;

see Figure 4

5 V

20

0

-

ns

10 V

20

0

-

ns

15 V

15

0

-

ns

tW

pulse width

nCP input LOW;

see Figure 4

5 V

60

30

-

ns

10 V

30

15

-

ns

15 V

20

10

-

ns

nSD input HIGH;

see Figure 5

5 V

50

25

-

ns

10 V

24

12

-

ns

15 V

20

10

-

ns

nCD input HIGH;

see Figure 5

5 V

50

25

-

ns

10 V

24

12

-

ns

15 V

20

10

-

ns