RIVA128ZX datasheet(37/85 Pages) STMICROELECTRONICS

37 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

37/85

6.4

LAYOUT OF FRAMEBUFFER CLOCK SIGNALS

Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of memory to give reduced

clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and FBCLKFB.

It is recommended that long traces are used without tunable components. If the layout includes provision

for expansion to 8MBytes, the clock path to the 4MByte parts should be at the end of the trace, and the

clock path to the 8MByte expansion located between the RIVA128ZX and the 4MByte parts as shown in

Figure 32. FBCLK2 and FBCLKFB should be shorted together as close to the package as possible.

Figure 32.

Recommended memory clock layout

6.5

FRAMEBUFFER INTERFACE TIMING SPECIFICATION

Figure 33.

SDRAM/SGRAM I/O timing diagram

Table 10.

SDRAM/SGRAM I/O timing parameters

Symbol

Parameter

Min.

Max.

Unit

Notes

-10

-12

-10

-12

tCK

CLK period

tCH

CLK high time

3.5

4.5

tCL

CLK low time

3.5

4.5

tAS

Address setup time

tAH

Address hold time

tDS

Write data setup time

RIVA128ZX

512K

x32

512K

x32

512K

x32

512K

x32

Bank 1

Bank 0

Expansion

to 8MBytes

FBCLK0

FBCLK1

FBCLK2

FBCLKFB

tCH

tCK

tCL

tAS,tDS

tAH,tDH

tLZ

tAC

tOH

FBCLKx

FBA[10:0], FBD[63:0]

FBD[63:0]

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