RIVA128ZX datasheet(35/85 Pages) STMICROELECTRONICS

35 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

35/85

6.3

SDRAM/SGRAM ACCESSES AND COMMANDS

Read and write accesses to SDRAM/SGRAM are burst oriented. SDRAM/SGRAM commands supported

by the RIVA128ZX are shown in Table 9. Initialization of the memory devices is performed in the standard

SDRAM/SGRAM manner. Access sequences begin with an Active command followed by a Read or Write

command. The address bits registered coincident with the Read or Write command are used to select the

starting column location for the burst access. The RIVA128ZX always uses a burst length of one and can

launch a new read or write on every cycle.

SDRAM/SGRAM has a fully synchronous interface with all signals registered on the positive edge of FB-

CLKx. Multiple clock outputs allow reductions in signal loading and more accuracy in data sampling at

high frequency. The clock signals can be interspersed as shown in Figure 30, page 33 for optimal loading

with either 4 or 8MBytes. The I/O timings relative to FBCLKx are shown in Figure 32, page 37.

Table 8.

Truth table of supported SDRAM commands

NOTES

FBCKE is high and DSF is low for all supported commands.

Activates or deactivates FBD[63:0] during writes (zero clock delay) and reads (two-clock delay).

For FBA10 low, FBCS[1]# determines which bank is precharged; for FBA10 high, all banks are precharged irrespective

of the state of FBCS[1]#.

Command1

FBCS0# FBRAS# FBCAS# FBWE#

FBDQM

FBCS[1]#,

FBA[10:0]

FBD[63:0] Notes

Command inhibit (NOP)

No operation (NOP)

Active (select bank and

activate row)

FBCS[1]#=bank

FBA[10:0]=row

Read (select bank and

column and start read

burst)

FBCS[1]#=bank

FBA[10]=0

FBA[7:0]=col

Write (select bank and

column and start write

burst)

FBCS[1]#=bank

FBA[10]=0

FBA[7:0]=col

valid data

Precharge (deactivate

row in bank or banks)

FBA[10]=code

Load mode register

LLLL

FBCS[1]#,

FBA[10:0] =

opcode

Write enable/output

enable

active

Write inhibit/output

High-Z

high-Z

RIVA128ZX bảng dữ liệu(PDF) 35 Page - STMicroelectronics

RIVA128ZX bảng dữ liệu(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

bảng dữ liệu tải về

Link URL