RIVA128ZX datasheet(31/85 Pages) STMICROELECTRONICS

31 / 85 page

128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX

31/85

6.1

SDRAM INTERFACE

Two extra address lines are required to support 8MByte SDRAM compared with those needed for 4MByte

SGRAM on RIVA 128. These are the A10 signal which was defined on the RIVA 128 pinout for future ex-

pansion and the SDRAM’s internal bank select address bit (BA signal). To provide this extra signal the

RIVA128ZX FBCS[1]# pin is internally redefined to be the SDRAM BA/A11 signal.

Since the RIVA128ZX supports a maximum addressable memory of 8MBytes, SDRAM support is only al-

lowed with a 64-bit data bus. Figure 28 shows an example SDRAM memory configuration for RIVA128ZX.

Note this figure attempts to scramble the bytes and data bits within bytes to simplify board layout, but this

will depend on how the board components are placed in the layout.

Figure 28.

8MByte SDRAM configuration using 16Mbit devices

FBD[127:0]

FBD[7:0]

FBDQM[3]#

FBDQM[0]#

FBDQM[5]#

FBDQM[6]#

FBDQM[1]#

FBDQM[2]#

FBDQM[4]#

FBDQM[7]#

FBCS[0]#

FBCLK1

FBCS[0]#

FBCLK0

FBCS[0]#

FBCLK1

FBCS[0]#

FBCLK0

×16

SDRAM

DQML

DQMH

CLK

×16

SDRAM

DQML

DQMH

CLK

×16

SDRAM

DQML

DQMH

CLK

×16

SDRAM

DQML

DQMH

CLK

FBD[31:24]

FBD[23:16]

FBD[15:8]

FBD[55:48]

FBD[47:40]

FBD[56:63]

FBD[32:39]

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