RX72N datasheet(140/179 Pages) RENESAS

140 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 140 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.13

SSIE

n = 0, 1

Note 1. The SSIE has a single path for transmission in slave mode. To generate the data for transmission, the signals input through the

SSILRCKn pin through the abovementioned path are used. After that, the data for transmission proceed to be used as the

logical outputs to the SSITXD0 or SSIDATA1 pin.

Figure 2.73

Clock Input Timing

Figure 2.74

SSIE Clock Input/Output Timing

Table 2.42

Expansion Serial Sound Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

AUDIO_CLK

Cycle

tEXcyc

—

Figure 2.73

High/low level

tEXL/tEXH

0.4

0.6

tEXcyc

SSIBCKn

Cycle

Master

—

Figure 2.74

Slave

—

Output clock high level

Master

tHC

0.35

—

Output clock low level

tLC

0.35

—

Input clock high level

Slave

tHC

0.35

—

Input clock low level

tLC

0.35

—

Output clock rise time

Master

tRC

—0.15

Output clock fall time

tFC

—0.15

Input clock rise time

Slave

tRC

—0.15

Input clock fall time

tFC

—0.15

SSILRCKn,SSITXD0,

SSIRXD0, SSIDATA1

Input setup time

Master

tSR

—

Figure 2.75,

Figure 2.76

Slave

—

Input hold time

Master

tHR

8—

Slave

—

Output delay time

Master

tDTR

–10

Slave

Output delay time from when an

SSILRCK0 signal is changed*1

Slave

tDTRW

—

Figure 2.77

AUDIO_CLK

(input)

tEXH

tEXf

tEXL

1/2 VCC

tEXcyc

tEXr

SSIBCKn

tHC

tLC

tRC

tI, tO

tFC

(n = 0, 1)

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