RX72N datasheet(43/179 Pages) RENESAS

43 / 179 page

RX72N Group

1. Overview

R01DS0343EJ0120 Rev.1.20

Page 43 of 179

Nov 15, 2023

Note 1. P53 is multiplexed with the BCLK pin function, so cannot be used as an I/O port pin when the external bus is enabled.

P54

D1[A1/D1]/

EDACK0/

ALE

MTIOC4B/

TMCI1

CTS2#/

RTS2#/

SS2#/

MOSIC-B/

CTX1

ET0_LINK

STA

LCD_DAT

A6-A

P55

D0[A0/D0]/

EDREQ0/

WAIT#

MTIOC4D/

TMO3

TXD7/

SMOSI7/

SSDA7/

MISOC-B/

CRX1

ET0_EXOU

LCD_DAT

A5-A

IRQ10

PC6

D2[A2/D2]/

A22/CS1#

MTIOC3C/

MTCLKA/

TMCI2/PO30/

TIC0

GTIOC3B RXD8/

SMISO8/

SSCL8/

SMISO10/

SSCL10/

RXD10/

MOSIA-A

ET0_ETXD

MMC_D6-A

LCD_DAT

A10-A

IRQ13

R10

PC5

D3[A3/D3]/

A21/CS2#/

WAIT#

MTIOC3B/

MTCLKD/

TMRI2/PO29

GTIOC1A SCK8/

RTS8#/

SCK10/

RSPCKA-A

ET0_ETXD

MMC_D5-A

LCD_DAT

A11-A

R11

PC3

A19

MTIOC4D/

TCLKB/PO24

GTIOC1B TXD5/

SMOSI5/

SSDA5

ET0_TX_E

QMO-A/QIO0-

A/SDHI_D0-A/

MMC_D0-A

LCD_DAT

A16-A

R12

PL4

GTADSM0 SSLC1

ET0_ETXD

RMII0_TXD

R13

P75

CS5#

PO20

SCK11/

RTS11#

ET0_ERXD

RMII0_RX

SDHI_D2-A/

MMC_RES#-A

LCD_DAT

A20-A

R14

P74

A20/CS4#

PO19

SS11#/

CTS11#

ET0_ERXD

RMII0_RX

LCD_DAT

A21-A

R15

PM5

GTADSM1

ET0_ETXD

SDHI_D3-D/

QIO3-A

Table 1.5

List of Pin and Pin Functions (224-Pin LFBGA) (11/11)

Number

Power

Supply

Clock

System

Control

I/O Port

Bus

EXDMAC

SDRAMC

Timer

Communication

Memory I/F

Camera I/F

GLCDC

Interrupt

A/D

D/A

224-Pin

LFBGA

(MTU, TPU,

TMR, PPG,

RTC, CMTW,

POE, CAC)

(GPTW,

POEG)

(SCI, RSPI,

RIIC, CAN,

USB, SSIE)

(ETHERC,

PMGI)

(QSPI, SDHI,

MMCIF, PDC)

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