FN8724 datasheet(23/34 Pages) RENESAS

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ISL98608IIH

FN8724 Rev.2.01

Page 23 of 33

Dec 7, 2021

VP/VN Output Hi-Z Mode

The ISL98608IIH VP and VN regulator can be configured in a Hi-Z

mode to prevent any leakage current flowing between VP and VN.

Using I2C register 0x05 <b6> can be used to disable the

pull-down resistors on VP and VN giving a “Hi-Z” state of output.

Power-On/Off Sequence

The boost regulator used to generate VP/VN, VBST, is activated

when the VIN input voltage is higher than the UVLO threshold,

and either ENP or ENN is high, along with their respective I2C

enable bits. To enable the VBST, Reg 0x05 <b0> should be 1

(by default this bit is set to 1). The VP output is activated if ENP is

high, VBST has completed its soft-start and Reg 0x05 <b2> is 1

(by default this bit is set to 1). The VN charge pump is activated

2ms after VBST has completed soft-start and the ENN has been

pulled high, whichever comes later. To activate the VN regulator,

Reg 0x05 <b1> should also be 1 (by default this bit is set to 1).

Figure 48 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

enabled in register 0x04 <b4> by writing “0” and VP soft-start

time is 1.2ms where as VN soft-start time is 1.8ms programmed

from register 0x05 <b7> by writing “1”. The VBST soft-starts if the

VIN voltage is higher than the UVLO threshold and either ENN or

ENP is high. When the VBST soft-start is completed, the VP

regulator soft-starts in 1.2ms. The VN power-on occurs 2ms after

VBST soft-start completes. The VN soft-start time takes 1.8ms.

The 2ms power-on delay between VP and VN can be disabled

from register 0x04 <b4> by writing “1”.

Figure 49 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

enabled in register 0x04 <b4> by writing “0” and VP/VN soft-start

time is programmed to 0.7ms from register 0x05 <b7> by writing

“1”. The VBST soft-starts if the VIN voltage is higher than the

UVLO threshold and either ENN or ENP is high. When the VBST

soft-start is completed, the VP regulator soft-starts in 0.7ms. The

VN power-on occurs 2ms after VBST soft-start completes. The VN

soft-start time takes 0.7ms. The 2ms power-on delay between VP

and VN can be disabled from register 0x04 <b4> by writing “1”.

Figure 50 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

disabled in register 0x04 <b4> by writing “1” and VP/VN soft-start

time is programmed to 1.2ms from register 0x05 <b7> by writing

“0”. The VBST soft-starts if the VIN voltage is higher than the

UVLO threshold and either ENN or ENP is high. When the VBST

soft-start is completed, the VP and VN regulator soft-starts in

1.2ms.

Figure 51 shows the power-on sequence for the case when the

ENP and ENN all are tied together and VP/VN rail sequencing is

disabled in register 0x04 <b4> by writing “1” and VP/VN soft-start

time is programmed to 0.7ms from register 0x05 <b7> by writing

“1”. The VBST soft-starts if the VIN voltage is higher than the

UVLO threshold and either ENN or ENP is high. When the VBST

soft-start is completed, the VP and VN regulator soft-starts in

0.7ms.

The VP/VN/VBST soft-start times quoted above (VBST = 0.47ms,

VP = 1.2ms and VN = 1.2ms or 1.8ms) are valid for the default

voltage levels (VSBT = 5.15V, VP = 5V and VN = -5V). These will

change with different voltages, as they are set to give a fixed

dv/dt.

Figure 52 shows the power-on sequence for the case when the

ENP and ENN are controlled by two GPIOs and VP/VN rail

sequencing is enabled from register 0x04 <b4> by writing "0".

Also, VP soft-start time is programmed to 1.2ms and VN

soft-start time is programmed to 1.8ms from register 0x05 <b7>

by writing "0".

ENP or ENN going low will shut down VP or VN, respectively. If

both ENP and ENN are pulled low, then VP, VN and VBST are all

turned off. The VN regulator shuts off when ENN is pulled low. VP

and VBST power-off occurs 2ms after the ENP signal goes low

(Register 0x05<b4> = 0), (see Figure 53). If Register 0x05<b4> = 1,

the VP and VN regulators will power off immediately when ENN

and ENP are pulled low (see Figure 54).

If VIN falls below UVLO while the IC is active, all active regulators

will be turned off at the same time (see Figure 55).

VP AND VN DISCHARGE RESISTOR

The integrated discharge resistors on the VP and VN outputs are

80Ω (typical) and 35Ω (typical), respectively. The VP discharge

resistor is enabled for 2ms (by default) following when ENN goes

low. If ENP is still high, the VP discharge resistor is disabled 2ms

after ENN goes low. The VP discharge resistor will be re-enabled

when ENP goes low. If the same output capacitor (value, size,

rating) is used for VN and VP, the VN rail will discharge faster

than VP if they are both turned off at the same time. This is ideal

for applications that require the VN rail to go down before VP at

power-off.

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