FN8724 datasheet(22/34 Pages) RENESAS

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ISL98608IIH

FN8724 Rev.2.01

Page 22 of 33

Dec 7, 2021

Display Power Supply Function

Description

Regulator Output Enable/Disable

The boost converter, VBST, will be enabled whenever either ENP

or ENN is HIGH and the VBST enable bit <b0> in the ENABLE

VN), ENN and ENP must be LOW, or its enable bit set to ‘0’.

The negative charge pump, VN, is enabled whenever ENN is HIGH

and the VN enable bit <b1> in the ENABLE register is set to ‘1’. To

disable, ENN must be LOW, or its enable bit set to ‘0’.

The LDO, VP, is enabled whenever ENP is HIGH and the VP enable

Bit <b2> in the ENABLE register is set to ‘1’. To disable ENP must

be LOW, or its enable bit set to ‘0’.

All the ENABLE register bits <b2:b0> are set to ‘1’ by default.

Note, ENP and ENN are logic level inputs with HIGH/LOW

thresholds defined by the VIH/VIL specifications, respectively.

These inputs also have 1MΩ (typical) internal pull-down

resistance to ground. If the pins are left at high-impedance, they

will default to a LOW logic state. Refer to the “LOGIC/DIGITAL” on

page 7 of the “Electrical Specifications” table for more

information.

VP and VN Headroom Voltage and Output

Current

The VP and VN headroom voltage is defined as the difference

between the VBST target voltage and maximum of VP and |VN|

target voltages.

The headroom voltage must be set high enough so that both the

VP LDO and VN negative Charge Pump (CP) can maintain

regulation. The VBST voltage must be greater than the absolute

value of the VN regulation voltage (i.e., the headroom voltage has

to be >0V). Primarily, the minimum headroom voltage is a

function of the maximum application load current that the IC will

need to support. Fast output current peaks of only a few

microseconds should not be considered - those instantaneous

current peaks will be supported by the output capacitors and not

by the regulator. Equation 4 shows the minimum headroom

required depending upon the current.

Note the headroom voltage should not be set overly high, since

increasing headroom generally yields lower efficiency

performance due to increased conduction losses.

For very low duty cycle where the output voltage of the VBST is

very close to the input voltage, VBST starts to track the input

voltage with a fixed headroom of ~600mV. This feature avoids

the minimum duty cycle limitation from producing increased

ripple on VBST (which feeds through to VP/VN) and ensures

proper regulation of the VBST, VP and VN regulators.

For most applications, the ISL98608IIH default 400mV

headroom voltage setting provides optimal performance for DC

output current up to 200mA (maximum).

Negative Charge Pump Operation (VN)

The ISL98608IIH uses a negative charge pump with internal

switches to create the VN voltage rail. The charge pump input

voltage VBSTCP comes from the boost regulator output, VBST.

Regulation is achieved through a classic voltage mode

architecture where an internally compensated integrator output

is compared with the voltage ramp to set a duty cycle. The duty

cycle controls the amount of time the output capacitor is charged

during each switching cycle. The maximum duty cycle is 50%.

The charge pump output capacitor (placed on the VN pin) is

pumped through internal current source to minimize system

noise.

VN and VBST PFM

The ISL98608IIH features light-load Pulse Frequency Modulation

(PFM) mode for both the boost regulator and the charge pump, to

maximize efficiency at light loads.

The device always uses PWM mode at heavy loading, but will

automatically switch to PFM mode at light loads to optimize

efficiency. PFM capability is enabled using the respective PFM

mode enable/disable register bits.

VBST PFM

In PFM mode, the boost can be configured to either use a fixed

peak current or to automatically select the optimal peak current

setting. The automatic, or “Auto” mode, is designed to

dynamically adjust the peak current to maintain boost output

voltage ripple at relatively fixed levels across input voltage, while

improving efficiency at low input voltages. This patent pending

architecture adjusts the peak current to keep the sum of inductor

ramp-up and ramp-down times to a constant value of

approximately 1.3*TPWM. This scheme also gives more

consistent ripple part-to-part and keeps PWM/PFM hysteresis

defined in a smaller and more optimal band across operating

voltages. It is recommended to operate the part in this mode.

The VBST PFM mode features an ultrasonic Audio Band

Suppression (ABS) mode, which prevents the switching

frequency from falling below 30kHz to avoid audible noise. When

the time interval between two consecutive switching cycles in

PFM mode is more than 33ms (i.e., 30kHz frequency) the

regulator reduces the peak inductor current, to maintain the

frequency at 30kHz. If this is not sufficient, the regulator will add

low current reverse current cycles.

VN PFM

The charge pump PFM mode works by increasing the minimum

pump on-time, and thereby the charge delivered per cycle, when

the load is low. This allows increased ripple to be traded off

against switching losses.

Headroom V

 Imax A

X2.7



(EQ. 4)

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