FN8724 datasheet(20/34 Pages) RENESAS

20 / 34 page

ISL98608IIH

FN8724 Rev.2.01

Page 20 of 33

Dec 7, 2021

All fault bits can be cleared by cycling VIN or with a software

reboot (clearing register 0x04 bit<b7>). This will reset the entire

part to default settings and disable all outputs until they have

sequenced up again.

ENABLE

The “ENABLE” register (Register Address 0x05) can be used to

control the enable/disable state of the boost (VBST), positive

LDO (VP) and negative charge pump (VN). This can also be used

to sequence the regulators. Refer to “Enable Timing Control

Options for VP and VN Regulators” on page 26 for details

regarding the control of output regulators using the enable and

I2C control. Using this register the VP and VN pull-down resistor

can be enabled or disabled, soft-start time of VP and VN can be

adjusted and the timing of VP sequencing can be adjusted.

Bit<4> of ENABLE register controls the delay between the ENP

signal going low and the VP regulator power-off. If Bit<4> is set to

0, the VP regulator is disabled 2ms after ENP going low. If Bit<4>

is set to 1, the VP regulator is disabled as soon as ENP goes low.

Bit<5> of ENABLE register controls shutdown behavior of VBST,

VP and VN regulators after OTP or UV event. If Bit<5> is set to 1,

then VBST, VP and VN regulators are shut off after OTP or UV

event. To turn on the regulators, IC should be out of fault

condition and ENP and ENN signals are recycled. Regulators can

also be turned on by recycling the enable bit in the I2C register. If

Bit<5> is set to 0, then regulators will turn back on as soon as

fault condition is removed.

Bit<6> controls the VN and VP discharge resistor. If Bit<6> is

programmed to “0”, then it will enable the discharge resistor

where as “1” will disable the discharge resistor.

Bit<7> controls the soft-start time of VN and VP regulators. If

Bit<7> is set to “0”, then soft-start time of VN is 1.8ms and for VP

is 1.2ms whereas when set to “1”, soft-start time of both VP and

VN regulator is 0.7ms.

VBST/VN/VN VOLTAGE

The output voltages of VBST, VP and VN regulators can be

changed using the registers “VBST Voltage”, “VP Voltage” and

“VN Voltage,” respectively. VBST voltage is at Register Address

0x06, VN voltage is at Register Address 0x08 and VP voltage is at

be changed from their default values using I2C.

• The VBST regulator can be programmed from +4.65V to +7.3V

• The VP regulator can be programmed from +4.5V to +7V

• The VN regulator can be programmed from -7V to -4.5V

• All are adjustable with 50mV step size.

Once the maximum VBST voltage (7.3V) is reached the algorithm

will wrap around to give VBST voltage from 4.65V to 5.1V.

Similarly, when maximum VP and VN voltage are reached (±7V),

the algorithm will wrap around to give VP/VN voltage from ±4.5V

to ±4.95V.

To determine the expected output voltage for a specific register

value, see the following section “Output Voltage Calculation for

VBST, VP and VN”.

NOTE: Output voltage registers should not be changed during their

respective soft-start sequence.

Output Voltage Calculation for VBST, VP and VN

The expected output voltage for each regulator can be

determined using Equations 1 through 3. Note, N is the 5-bit

The expected VBST voltage can be determined using Equation 1.

Once the maximum VBST voltage is reached, the algorithm will

wrap around to give VBST voltage from 4.65V to 5.1V.

The expected VP voltage can be determined using Equation 2.

Once the maximum VP voltage is reached, the algorithm will

wrap around to give VP voltage from 4.50V to 4.95V.

The expected VN voltage can be determined using Equation 3.

Once the minimum VN voltage is reached, the algorithm will

wrap around to give VN voltage from -4.50V to -4.95V.

Example Calculations:

If N = 10 (decimal) VBST(Default) = 5.15V, VP/VN(Default) = ±5V:

The default output voltage of VBST, VP, and VN regulators can be

determined by factory configurable settings. The output voltage

can be changed using I2C control when VIN > POR (Power-On

Reset) voltage. When powered up, Registers 0x06, 0x08, and

0x09 read value 0x00 and VBST, VN, VP voltage levels are at

respective default voltage. Using I2C control, the voltage can be

changed by changing the value of Registers 0x06, 0x08, and

0x09. As VIN < POR (Power-On Reset) voltage, Registers 0x06,

0x08, and 0x09 read 0x00.

VBST CONTROL

In addition to output voltage adjustments, key operation

parameters can be changed using I2C to optimize the

ISL98608IIH performance.

The “VBST CNTRL and VBST/VN Frequency” register (Register

Address 0x0D) can be used to control boost PFM mode, boost

FET slew rate and switching frequency of the boost and charge

pump.

VBST V



VBST Default

VN 50mV



(EQ. 1)

VP V



VP Default



ꞏ

VN 50mV



(EQ. 2)

VN V



VN Default



ꞏ

VN 50mV



–

(EQ. 3)

VBST V



5.15V 10 50mV



5.65V

VP V



5V 10 50mV



5.5V

VN V



-5V 10 50mV



–

-5.5V

FN8724 bảng dữ liệu(PDF) 20 Page - Renesas Technology Corp

FN8724 bảng dữ liệu(HTML) 20 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL