MPC8313E datasheet(17/92 Pages) FREESCALE

tên linh kiện	MPC8313E

Giải thích chi tiết về linh kiện	PowerQUICC??II Pro Processor Hardware Specifications

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 19 provides the input AC timing specifications for the DDR2 SDRAM interface.

Figure 3 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.

Figure 3. DDR Input Timing Diagram

Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions. with GVDD of 2.5 ±5%

Parameter

Symbol

Min

Max

Unit

Notes

Controller Skew for MDQS—MDQ

tCISKEW

——

1, 2

333 MHz

—

–750

750

—

266 MHz

—

–750

750

—

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is

captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the

absolute value of tCISKEW.

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

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