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MPC8313E bảng dữ liệu(PDF) 31 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8313E
Giải thích chi tiết về linh kiện  PowerQUICC??II Pro Processor Hardware Specifications
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MPC8313E bảng dữ liệu(HTML) 31 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
31
Ethernet: Three-Speed Ethernet, MII Management
8.4.2
MII Management AC Electrical Specifications
Table 33 provides the MII management AC timing specifications.
Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V) NVDDA/NVDDB
—
2.97
3.63
V
Output high voltage
VOH
IOH = –1.0 mA
NVDDA or NVDDB = Min
2.10
NVDDA +0.3
or
NVDDB +0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDDA or LVDDB = Min
VSS
0.50
V
Input high voltage
VIH
—2.0
—
V
Input low voltage
VIL
——
0.80
V
Input high current
IIH
NVDDA or NVDDB = Max
VIN
1 = 2.1 V
—
40
μA
Input low current
IIL
NVDDA or NVDDB = Max
VIN = 0.5 V
–600
—
μA
Note:
1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 33. MII Management AC Timing Specifications
At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 10% or 2.5 V ± 5%
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
—
ns
—
MDC to MDIO delay
tMDKHDX
10
—
170
ns
—
MDIO to MDC setup time
tMDDVKH
5—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0—
—
ns
—
MDC rise time
tMDCR
—
—
10
ns
—
MDC fall time
tMDHF
—
—
10
ns
—
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).



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