C8051F310 datasheet(152/228 Pages) SILABS

152 / 228 page

C8051F310/1/2/3/4/5/6/7

152

Rev. 1.7

SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration

Bit7:

ENSMB: SMBus Enable.

This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-

itors the SDA and SCL pins.

0: SMBus interface disabled.

1: SMBus interface enabled.

Bit6:

INH: SMBus Slave Inhibit.

When this bit is set to logic 1, the SMBus does not generate an interrupt when slave events

occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are

not affected.

0: SMBus Slave Mode enabled.

1: SMBus Slave Mode inhibited.

Bit5:

BUSY: SMBus Busy Indicator.

This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0

when a STOP or free-timeout is sensed.

Bit4:

EXTHOLD: SMBus Setup and Hold Time Extension Enable.

This bit controls the SDA setup and hold times according to Table 14.2.

0: SDA Extended Setup and Hold Times disabled.

1: SDA Extended Setup and Hold Times enabled.

Bit3:

SMBTOE: SMBus SCL Timeout Detection Enable.

This bit enables SCL low timeout detection. If set to logic 1, the SMBus forces Timer 3 to

reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is con-

figured in split mode (T3SPLIT is set), only the high byte of Timer 3 is held in reload while

SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the

Timer 3 interrupt service routine should reset SMBus communication.

Bit2:

SMBFTE: SMBus Free Timeout Detection Enable.

When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high for

more than 10 SMBus clock source periods.

Bits1–0: SMBCS1-SMBCS0: SMBus Clock Source Selection.

These two bits select the SMBus clock source, which is used to generate the SMBus bit

rate. The selected device should be configured according to Equation 14.1.

R/W

Reset Value

ENSMB

INH

BUSY

EXTHOLD SMBTOE SMBFTE SMBCS1

SMBCS0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xC1

SMBCS1

SMBCS0

SMBus Clock Source

Timer 0 Overflow

Timer 1 Overflow

Timer 2 High Byte Overflow

Timer 2 Low Byte Overflow

C8051F310 bảng dữ liệu(PDF) 152 Page - Silicon Laboratories

C8051F310 bảng dữ liệu(HTML) 152 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL