C8051F310 datasheet(149/228 Pages) SILABS

149 / 228 page

Rev. 1.7

149

C8051F310/1/2/3/4/5/6/7

14.4. Using the SMBus

The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-

trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides

the following application-independent features:

•

Byte-wise serial data transfers

•

Clock signal generation on SCL (Master Mode only) and SDA data synchronization

•

Timeout/bus error recognition, as defined by the SMB0CF configuration register

•

START/STOP timing, detection, and generation

•

Bus arbitration

•

Interrupt generation

•

Status information

SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,

this interrupt is generated after the ACK cycle so that software may read the received ACK value; when

receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing

ACK value. See Section “14.5. SMBus Transfer Modes” on page 157 for more details on transmission

sequences.

Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or

the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control

“14.4.2. SMB0CN Control Register” on page 153; Table 14.4 provides a quick SMB0CN decoding refer-

ence.

SMBus configuration options include:

•

Timeout detection (SCL Low Timeout and/or Bus Free Timeout)

•

SDA setup and hold time extensions

•

Slave event enable/disable

•

Clock source selection

These options are selected in the SMB0CF register, as described in Section “14.4.1. SMBus Configura-

tion Register” on page 150.

C8051F310 bảng dữ liệu(PDF) 149 Page - Silicon Laboratories