DRA752ABC datasheet(202/443 Pages) TI2

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202

DRA756, DRA755, DRA754, DRA752

DRA751, DRA750, DRA746, DRA745, DRA744

SPRS950F – DECEMBER 2015 – REVISED MAY 2019

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Timing Requirements and Switching Characteristics

7.1

Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions

unless otherwise specified.

7.2

Interface Clock Specifications

7.2.1

Interface Clock Terminology

The interface clock is used at the system level to sequence the data and/or to control transfers accordingly

with the interface protocol.

7.2.2

Interface Clock Frequency

The two interface clock characteristics are:

•

The maximum clock frequency

•

The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the Device IC and does not take into account any system consideration

(PCB, peripherals).

The system designer will have to consider these system considerations and the Device IC timing

characteristics as well to define properly the maximum operating frequency that corresponds to the

maximum frequency supported to transfer the data on this interface.

7.3

Timing Parameters and Information

The timing parameter symbols used in the timing requirement and switching characteristic tables are

created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other

related terminologies have been abbreviated as follows:

Table 7-1. Timing Parameters

SUBSCRIPTS

SYMBOL

PARAMETER

Cycle time (period)

Delay time

dis

Disable time

Enable time

Hold time

Setup time

START

Start bit

Transition time

Valid time

Pulse duration (width)

Unknown, changing, or don't care level

Fall time

High

Low

Rise time

Valid

Invalid

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