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MPC8309CVMADFC bảng dữ liệu(PDF) 48 Page - NXP Semiconductors

tên linh kiện MPC8309CVMADFC
Giải thích chi tiết về linh kiện  PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications
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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
48
Freescale Semiconductor
JTAG
The following figure shows the SPI timing in slave mode (external clock).
Figure 37. SPI AC Timing in Slave Mode (External Clock) Diagram
The following figure shows the SPI timing in master mode (internal clock).
Figure 38. SPI AC Timing in Master Mode (Internal Clock) Diagram
21 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG)
interface of the MPC8309.
21.1
JTAG DC Electrical Characteristics
The following table provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface
of the MPC8309.
Table 53. JTAG Interface DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH =–6.0mA
2.4
—
V
Output low voltage
VOL
IOL =6.0 mA
—
0.5
V
Output low voltage
VOL
IOL =3.2 mA
—
0.4
V
SPICLK (Input)
tNEIXKH
tNEIVKH
tNEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note:
The clock edge is selectable on SPI.
SPICLK (Output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note:
The clock edge is selectable on SPI.
tNIIVKH



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