MPC8309CVMADFC datasheet(16/81 Pages) NXP

16 / 81 page

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

DDR2 SDRAM

The following figure shows the input timing diagram for the DDR controller.

Figure 4. DDR Input Timing Diagram

6.2.2

DDR2 SDRAM Output AC Timing Specifications

The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.

Table 15. DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of 1.8V ± 100mV.

Parameter

Symbol

Min

Max

Unit

Note

Controller skew for MDQS—MDQ/MDM

tCISKEW

1, 2

266 MHz

–750

750

Notes:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute

value of tCISKEW.

Table 16. DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of 1.8V ± 100mV.

Parameter

Symbol1

Min

Max

Unit

Note

MCK cycle time, (MCK/MCK crossing)

tMCK

5.988

ADDR/CMD output setup with respect to MCK

tDDKHAS

333 MHz

266 MHz

2.4

2.5

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

333 MHz

266 MHz

2.4

2.5

—

MCK[n]

tMCK

MDQ[x]

MDQS[n]

tDISKEW

MPC8309CVMADFC bảng dữ liệu(PDF) 16 Page - NXP Semiconductors

MPC8309CVMADFC bảng dữ liệu(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

bảng dữ liệu tải về

Link URL