MPC8309CVMADFC datasheet(14/81 Pages) NXP

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3

Freescale Semiconductor

DDR2 SDRAM

The following table provides the PLL lock times.

5.1

Reset Signals DC Electrical Characteristics

The following table provides the DC electrical characteristics for the MPC8309 reset signals mentioned in

Table 9.

6DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the

MPC8309. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V.

6.1

DDR2 SDRAM DC Electrical Characteristics

The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)

of the MPC8309 when GVDD(typ) = 1.8 V.

The following table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET

4—

tSYS_CLK_IN

1, 2

Input hold time for POR config signals with respect to negation of

HRESET

—

1, 2

Notes:

1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8309 PowerQUICC

II Pro Integrated Communications Processor Family Reference Manual

2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].

Table 10. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Note

PLL lock times

—

100

s—

Table 11. Reset Signals DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Note

Output high voltage

VOH

IOH = –6.0 mA

2.4

—

Output low voltage

VOL

IOL = 6.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

—

Input current

IIN

0 V

 VIN  OVDD

—

±5

A—

Note:

1. This specification applies when operating from 3.3 V supply.

Table 9. RESET Initialization Timing Specifications (continued)

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