DM505LRBABF datasheet(142/295 Pages) TI2

142 / 295 page

GPMC_FCLK

gpmc_csi

gpmc_ben0

gpmc_

_ale

advn

gpmc_oen_ren

gpmc_wen

gpmc_ad[15:0]

DATA

GNF0

GNF1

GNF4

GNF6

GNF9

GNF3

GPMC_16

GPMC_FCLK

gpmc_csi

gpmc_ben0

gpmc_

_ale

advn

gpmc_oen_ren

gpmc_ad[15:0]

gpmc_waitj

DATA

GNF10

GNF13

GNF14

GNF15

GNF12

GPMC_15

142

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

Figure 5-36. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)

(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional

clock edge. GNF12 value must be stored inside AccessTime register bits field.

(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.

Figure 5-37. GPMC / NAND Flash - Data Write Cycle Timing(1)

(1) In gpmc_csi, i = 0 to 7.

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and

DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presented Table 4-28 and described in Device TRM, Control

Module section.

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