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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DAC38RF86 bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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DAC38RF86 bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 147 page  13 DAC38RF86, DAC38RF96 DAC38RF87, DAC38RF97 www.ti.com SLASEF4B – FEBRUARY 2017 – REVISED JULY 2017 Product Folder Links: DAC38RF86 DAC38RF96 DAC38RF87 DAC38RF97 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.6 Electrical Characteristics - Digital Specifications Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CML SerDes INPUTS: RX[7:0]+/- VDIFF Receiver input amplitude 50 1200 mV VCOM Input common mode voltage TERM = 111 600 mV TERM = 001 700 TERM = 100 0 TERM = 101 250 ZDDIFF Internal differential termination 85 100 115 Ω fSerDes SerDes bit rate 0.78125 12.5 Gbps DIFFERENTIAL CLOCK INPUTS: SYSREF+/-, DACCLK+/- fDACCLK DACCLK input frequency 0.1 9 GHz VCOM Differential input common mode voltage 0.5 V VI(DPP) Differential input peak-to-peak voltage 800 2000 mV ZT Internal termination 100 Ω CL Input capacitance 2 pF Duty cycle (DACCLK only) 40% 60% LVDS OUTPUT: SYNC0+/-, SYNC1+/- VCOM Output common mode voltage 1.2 V ZT Internal termination 100 Ω VOD Differential output voltage swing 500 mV CML OUTPUT: CLKTX+/- VOD CML OUTPUT: CLKTX+/- 1300 mV CMOS INTERFACE: SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM, RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST, TESTMODE, SYNCSE1, SYNCSE2 VIH High-level input voltage 0.7 x VDDIO V VIL Low-level input voltage 0.3 x VDDIO V IIH High-level input current –40 40 µA IIL Low-level input current –40 40 µA CI CMOS input capacitance 2 pF VOH High-level output voltage ILOAD = –100 µA VDDIO – 0.2 V ILOAD = –2 mA 0.8 x VDDIO VOL Low-level output voltage ILOAD = 100 µA 0.2 V ILOAD = 2 mA 0.5 LATENCY RX SerDes Digital Delay full rate, RATE = “00” 34 UI half rate, RATE = “01” 29 quarter rate, RATE = “10” 26.5 eighth rate, RATE = “11” 26.25 SerDes output to JED204B elastic buffer input latency 21 - 39 JESD clock cycles |
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